Half Adder & Full Adder Circuits using Logic Gates
Description
Trainer for binary half adder, full adder (using two half
Specifications
| DC BIAS | +5 V regulated |
|---|---|
| LOGIC HIGH | +5 V (Logic 1) |
| LOGIC LOW | 0 V (Logic 0) |
| OUTPUT INDICATION | LED for HIGH / LOW logic states |
| COMBINATIONAL CIRCUITS | Multiplexer, demultiplexer, encoder, decoder |
| SEQUENTIAL CIRCUITS | SR, D, JK, T flip-flops; registers and counters |